This relates generally to integrated circuits, and more particularly, to integrated circuits with clock generation circuitry.
Integrated circuits often include clock generation circuitry such as phase-locked loops (PLLs). A phase-locked loop typically has an input that receives a reference clock signal and has outputs at which multiple clocks signals are provided. The multiple clocks signals generated at the outputs of the phase-locked loop can exhibit clock rates that are integer multiples of the clock rate of the input reference clock signal.
The clock signals generated using the phase-locked loop can be distributed to different regions of an integrated circuit on which the phase-locked loop is formed using clock distribution circuitry. The clock distribution circuitry includes series-connected clock buffers (i.e., clock buffers connected serially in a chain) through which the clock signals are passed. These buffers are typically designed to provide equal rise times and fall times (i.e., equal rising and falling transition delays). A buffer exhibiting equal rise/fall times can be used to preserve the duty cycle of a clock signal that passes through that buffer. For example, a clock signal having 50% duty cycle that is received by a buffer exhibiting equal rise/fall times will exhibit 50% duty cycle at that buffer's output.
In practice, however, buffers and other circuits that are used to propagate clock signals may suffer from process, voltage, and temperature variations and may therefore exhibit unequal rise and fall times (i.e., mismatched rising and falling transition delays). Clock signals passing through buffers with mismatched rise/fall times will suffer from duty cycle distortion. For example, a clock signal having 50% duty cycle that is received by a buffer exhibiting mismatched rise/fall times may exhibit 60% duty cycle at that buffer's output.
Clock buffers are typically designed to provide stronger pull-up drive strengths and relatively weaker pull-down drive strengths. Clock signals passing through such types of clock buffers may experience fast rising transitions and relatively slower falling transitions. As a result, the duty cycle of the clock signals tend to increase as they are passed through each successive clock buffer. In some scenarios, clock signals that originally exhibit 50% duty cycle (i.e., clock signals that exhibit 50% duty cycle at the output of the phase-locked loop) may gradually approach 100% duty cycle as they are propagated through the clock buffer chain and may eventually be stuck high, thereby rendering the integrated circuit inoperable.